Dynamic CMOS Transmission Gate Logic

 

Dynamic CMOS Transmission Gate Logic: 

Each transmission gate is controlled by the clock signal and its complement. Therefore, the two-phase clocking need four clock signals. As in the nMOS structures, the CMOS dynamic circuit relies on charge storage in parasitic input capacitances during the inactive clock cycles.

Dynamic CMOS Transmission Gate Logic-Shift Register: A dynamic shift register circuit is provided which comprises an input terminal; an output terminal; first transfer gate means connected to the input terminal for receiving an input signal and transferring the input signal under the control of a first clock signal. 

The basic building block of the shift register consists of a CMOS inverter, which is driven by a TG.CK=1 Vin is transferred onto the parasitic input capacitance CX. The low on resistance of TG results in:

1.     A smaller transfer time compared to nMOS-only switches.

2.     No threshold voltage drop across TG.

  Dynamic CMOS Precharge-Evaluate Logic: The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B).

The capacitor, which represents the load capacitance of this gate, becomes charged. Because the 

transistor at the bottom is turned off, it is impossible for the output to be driven low during this 

phase. During the evaluation phase, Clock is high. If A and B are also high, the output will be 

pulled low. Otherwise, the output stays high (due to the load capacitance).