High Performance Dynamic CMOS Circuit

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High Performance Dynamic CMOS Circuit:

Domino CMOS Logic:

Domino CMOS logic circuits which are commonly used in high performance microprocessors for their high speed and area characteristics, are highly sensitive to noise as compared to static gates.
Domino logic is a CMOS-based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing.

A buffer, is a basic logic gate that passes its input, unchanged, to its output. Its behavior is the opposite of a NOT gate. The main purpose of a buffer is to regenerate the input, usually using a strong high and a strong low. A buffer has one input and one output; its output always equals its input.

Domino Logic Buffer



Here we describe CMOS as by given below diagram which consist of cascading of CMOS inverter static stage.

During the precharge phase the output node of the dynamic CMOS stage is activated to a high logic level, and the output of the CMOs becomes 0. When the clock rises, there are two possibilities: 
The output node of the dynamic CMOS stage is either discharged to a low level through the nMOS circuitry or it remains high Consequently,   input voltages applied to the dynamic CMOS stage, it is not possible for the buffer output to make a I to transition during the evaluation phase.

NORA CMOS Logic (NP-Domino Logic):

 NORA or np-CMOS design style has been proposed as a race-free dynamic CMOS technique for pipelined circuits. NORA logic is constructed of cascaded nMOS and pMOS dy- namic logic networks that end on latches.

In domino logic, an inverter is required to connect, while NORA logic consist of alternating nMOS and pMOS stages . The precharge and evaluate timing of nMOS logic stage is accomplished by clock signal ‘ϕ’ while pMOS logic stages are controlled by ϕ ̅.

 Operation:-

  • When ϕ=0, the output nodes of nMOS logic blocks are precharge to VDD through pMOS precharge transistor, whereas the output nodes of pMOS logic blocks are pre-charged to 0V through the nMOS discharge transistor, driven by ϕ.
  • When ϕ=1, all cascaded nMOS and pMOS logic stages evaluate one after the other. 

 From these above circuits which we studied today we summarize that:

• Full complementary static logic is best option in the majority of CMOS circuits.

      •   Noise-immunity is not sensitive to kn/kp
      •  Does not involve precharge of nodes        
      •  Dissipate no DC power
      •  Layout can be automated
      •  Slower and higher dynamic power dissipation than alternatives
      •  No clock 
    • Pseudo-nMOS static logic finds widest utility in large fan-in NOR gates.
      • Require only N+1 transistors for N fan-n.
      • Faster and lower dynamic power dissipation than full CMOS
      • Noise immunity sensitive to kn/kp
      • Dissipate DC power when pulled down       
      • No clock
    • CMOS domino logic should be used for low-power, high speed applications.
      • Require only N+k transistors for N fan-in, size advantages of pseudo-nMOS.
      • Dissipate no DC power
      • Noise immunity is not sensitive to kn/kp
      • Use of clocks enables synchronous operation
      • Rely on storage on soft node
      • Some of the speed advantage over static gates is diminished by the required per-charge (pre-discharge) time.

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