Basic Information on Dynamic Logic

Dynamic Logic

In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.

Dynamic logic circuits offer several significant advantages over static logic circuits.The operation of all dynamic logic gates depends on temporary storage of charge in parasitic node capacitances, instead of relying on steady-state circuit behavior.

Dynamic logic circuits require periodic clock signals in order to control charge refreshing.The capability of temporary storing a state, at a capacitive node allows us to implement very simple sequential circuits with memory functions. 

Common clock signals synchronize the operation of various circuit blocks. Power consumption increases with the parasitic capacitances.Therefore dynamic circuit implementation in smaller area, consumes less power than the static logic.

Dynamic CMOS logic circuits are mostly used in VLSI chips. It provides highest performance compared to different logic families like TTL, ECL. The noise tolerance of dynamic CMOS logic gates can be improved because of its faster speed and compact area than the static logic gates.

 To improve the noise immunity of circuit, the performance of feedback keeper and conditional keeper are optimized. The area, average power, delay and mean noise amplitude of the circuits are reduced. 

Author-Sahil Gupta